The present invention relates to depletion type MOS semiconductor devices that are suitably integrated with vertical MOSFET, and also relates to MOS power IC in which the depletion type MOS semiconductor devices are mounted, and a method of using the MOS power IC.
Where a MOS semiconductor apparatus using a MOS semiconductor device, such as IGBT, as an output-stage semiconductor device is employed for use with an inductive load, such as an ignitor switching circuit (for intermitting current through the primary winding of an ignition coil of an automobile, for example), the IGBT suffers from oscillation of its collector voltage. To overcome this problem, the inventors of the present invention proposed that a branch of series-connected constant-current device and resistor be provided between the collector and gate of the output-stage IGBT, as disclosed in laid-open Japanese Patent Publication (Kokai) No. 9-280147.
FIG. 19 is a circuit diagram (FIG. 1 of JP-A-9-280147) showing the configuration of the MOS semiconductor apparatus disclosed in the above publication. One of its output terminals (C) is connected to a primary winding of an ignition coil that is not illustrated. A branch in which a constant-current device 308 and a resistor 309 are connected in series is provided between the collector (cm) and gate (gm) of an output-stage IGBT 303. FIG. 21 shows output characteristics of this MOS power IC, wherein the horizontal axis represents the collector voltage of the IGBT, and the vertical axis represents the collector current. It is to be particularly noted that an unsaturated region of the constant-current device 308 is utilized to provide a characteristic that the collector current increases with an increase in the collector voltage, thereby to suppress oscillation of the collector voltage. In the above-identified publication, it is suggested to use a depletion type MOSFET or IGBT as the constant-current device 308, and fabricate or build this device into a part of the output-stage IGBT 303, but there is no specific description of such an integrated structure. It is also stated in the above publication that the constant-current device 308 may be in the form of a series power supply.
FIG. 20 is a cross-sectional view of a part of IGBT with which a depletion type and an enhancement type MOSFETs are integrated. The right-hand side portion of FIG. 20 illustrates an output-stage IGBT 320 epitaxial wafer is generally used in which an n+ buffer layer 322 and an nxe2x88x92 drift layer 323 are laminated on a pxe2x88x92 substrate 321, and a multiplicity of IGBT units are formed in a surface layer of the nxe2x88x92 drift layer 323. On the left-hand side of FIG. 20, a depletion type MOSFET 340 is formed on and within a pxe2x88x92 well region 333 that is formed in a surface layer of the nxe2x88x92 drift layer 323. The middle portion of FIG. 20 illustrates an enhancement-type n-channel MOSFET formed on and within the p well region 333, which is not related to the principle of the present invention.
To provide the depletion MOSFET 330, an nxe2x88x92 depletion region 334, n+ source region 335 and an n+ drain region 336 are formed in a surface layer of the pxe2x88x92 well region 333, such that the n+ source region 335 and n+ drain region 336 are located on the opposite sides of the nxe2x88x92 depletion region 334. A gate electrode layer 338 is formed above the nxe2x88x92 depletion region 334 with a gate insulating film 337 interposed therebetween. Source electrode 341 and drain electrode 342 are formed in contact with the n+ source region 335 and n+ drain region 336, respectively, such that the source electrode 341 also contact with the gate electrode layer 338.
With the arrangement as shown in FIG. 20, the constant-current device in the form of the depletion MOSFET 330 can be integrated with the IGBT on the same chip. As is understood from FIG. 19, the breakdown voltage of the constant-current device 308 is desirably equivalent to that of the IGBT 303 since these devices have a common output terminal (C). It is, however, extremely difficult for the lateral MOSFET formed in the pxe2x88x92 well region 333 as shown in FIG. 20, to achieve such a high breakdown voltage as several hundreds of voltage. Accordingly, the semiconductor apparatus having the circuit configuration of FIG. 19 must use a discrete high-voltage constant-current device or a power supply.
It is therefore an object of the present invention to provide a depletion type MOS semiconductor device that is suitably integrated with a vertical MOS type semiconductor apparatus, assuring a high breakdown voltage, and to provide a MOS power IC in which the depletion type MOS semiconductor device is mounted.
To accomplish the above object, the present invention provides a depletion type MOS semiconductor device which comprises: an nxe2x88x92 drift layer; a pxe2x88x92 well region formed in a surface layer of the nxe2x88x92 drift layer; an n+ emitter region formed in a surface layer of the pxe2x88x92 well region; an nxe2x88x92 depletion region formed in the surface layer of the pxe2x88x92 well region, to extend from the n+ emitter region to a surface layer of the nxe2x88x92 drift layer; a gate electrode layer formed on a gate insulating film, over the nxe2x88x92 depletion region; an emitter electrode formed in contact with surfaces of both the n1 emitter region and the pxe2x88x92 
well region; and a collector electrode formed on a rear surface of the nxe2x88x92 drift layer.
A p+ collector layer may be formed on the rear surface of the nxe2x88x92 drift layer, such that the collector electrode is held in contact with the p+ collector layer.
The depletion type MOS semiconductor device constructed as described above is suitably integrated with a vertical MOSFET, or a vertical IGBT in which the collector electrode contacts with the p+ collector layer, and exhibits a sufficiently high breakdown voltage that is equivalent to that of the MOSFET or IGBT.
In one preferred form of the invention, the pxe2x88x92 well region is formed at a substantially middle portion thereof with an aperture, so as to surround the nxe2x88x92 depletion region. With this arrangement, the entire area of the nxe2x88x92 drift layer inside the aperture is occupied by depletion layers that spread from the pxe2x88x92 well region, whereby the breakdown voltage of the device can be easily increased.
If a plurality of depletion type MOS semiconductor devices each constructed as described above are arranged in parallel with each other, the resulting MOS semiconductor apparatus provides a sufficiently large current capacity.
The pxe2x88x92 well regions of the depletion type MOS semiconductor devices connected in parallel with each other may be connected with each other. In this case, the plural MOS semiconductor devices may be formed over a reduced area of the semiconductor substrate, as compared with the case where the individual devices are formed separately, and a common electrode may be used for these semiconductor devices.
A plurality of nxe2x88x92 depletion regions may be formed in the nxe2x88x92 drift layer surrounded by one pxe2x88x92 well region. The depletion type MOS semiconductor apparatus thus constructed also provides a large current capacity.
In another preferred form of the invention, the nxe2x88x92 drift layer surrounded by one pxe2x88x92 well region assumes a substantially rectangular shape, and the length x of the short side of the rectangular shape is not greater than two-thirds of the thickness of the nxe2x88x92 drift layer.
As will be understood from experiment results as indicated later, the breakdown voltage is undesirably reduced if the length x of the short side exceeds two-thirds of the thickness of the nxe2x88x92 drift layer, probably because depletion layers that spread from opposite pxe2x88x92 well regions will not be joined together.
The length x of the short side is preferably not small than one-sixth of the thickness of the nxe2x88x92 drift layer. If the length x is smaller than one-sixth of the thickness of the nxe2x88x92 drift layer, a series resistance similar to a junction type FET becomes excessively large, and the resultant device will not be suited for practical use.
In a further preferred form of the invention, a pxe2x88x92 isolation well region is formed adjacent to the pxe2x88x92 well region, in the surface layer of the nxe2x88x92 drift layer, such that the potential of the pxe2x88x92 well region is independent of that of the pxe2x88x92 isolation well region. With this arrangement, the potential of the pxe2x88x92 well region may be freely set to a desired level, independently of the potential of the pxe2x88x92 isolation well region.
In a still further preferred form of the invention, a pxe2x88x92 isolation well region is formed adjacent to the pxe2x88x92 well region, in the surface layer of the nxe2x88x92 drift layer, and an isolated gate electrode layer is formed on an insulating film, over a surface of the nxe2x88x92 drift layer between the pxe2x88x92 well region and the pxe2x88x92 isolation well region. With this arrangement, conduction between the pxe2x88x92 well region and the pxe2x88x92 isolation well region can be prevented by applying a certain voltage to the isolated gate electrode layer.
The isolation gate electrode layer preferably has a potential close to that of the emitter electrode, or has the same potential as the emitter electrode. In this case, conduction between the pxe2x88x92 well region and the adjacent pxe2x88x92 isolation well region can be prevented.
Furthermore, the emitter electrode may be connected to the gate electrode. In this case, the potential of the gate electrode becomes equal to that of the emitter electrode, thereby providing a constant-current characteristic.
A MOS power IC in which the depletion type MOS semiconductor device as described above is mounted is provided which comprises: an output-stage MOS semiconductor device including a control portion of a metal-oxide-semiconductor (MOS) structure that provides a main gate (gm) as a control input port, a collector (cm) as an output port, and a main emitter (em); first and second output terminals (C,E) connected to the collector (cm) and the main emitter (em) of the output-stage semiconductor device; a control input terminal (G) connected to the main gate (gm) of the output-stage semiconductor device; a depletion type MOS semiconductor device that is connected in series with a collector resistance (Rc), a branch including the depletion type MOS semiconductor device and the collector resistance (Rc) being provided between the first output terminal (C) and the control input terminal (G), such that a collector (cd) of the depletion type MOS semiconductor device is connected to the C terminal.
In the MOS power IC constructed as described above, the output-stage MOS semiconductor device can be integrated with the depletion type MOS semiconductor device having substantially the same breakdown voltage as the output-stage MOS device, and the potential of the main gate (gm) of the output-stage MOS semiconductor device can be increased with an increase in the potential of the output terminal (C).
In another form of the MOS power IC, a gate resistance (RG1, RG2) is connected between the main gate (gm) of the output-stage MOS semiconductor device and the control input terminal (G), and the depletion type MOS semiconductor device is provided between the first output terminal (C) and one side of the gate resistance (RG2) close to the main gate (gm) of the gate resistance (RG1), such that the collector (cd) of the depletion type MOS semiconductor device is connected to the C terminal. In this MOS power IC, too, the output-stage MOS semiconductor device can be integrated with the depletion type MOS semiconductor device having substantially the same breakdown voltage as the output-stage MOS device, and the potential of the main gate (gm) of the output-stage MOS semiconductor device can be increased with an increase in the potential of the output terminal (C).
In a further form of the MOS power IC, a gate resistance (RG2) is connected between the main gate (gm) of the output-stage MOS semiconductor device and the control input terminal (G), and a branch in which a depletion type MOS semiconductor device that is connected in series with a collector resistance (RCG) is provided between the first output terminal (C) and the gate resistance (RG2), such that the collector (cd) of the depletion type MOS semiconductor device is connected to the output terminal (C).
In the MOS power IC as described above, too, the output-stage MOS semiconductor device can be integrated with the depletion type MOS semiconductor device having substantially the same breakdown voltage as the output-stage MOS device, and the potential of the main gate (gm) of the output-stage MOS semiconductor device can be increased with an increase in the potential of the output terminal (C).
If the collector resistance (RCG) is formed from a polysilicon layer that is insulated from a semiconductor substrate, the MOS power IC does not suffer from latch-up of a parasitic thyristor that would occur in the case where the collector resistance (RCG) if formed in the semiconductor substrate.
In the MOS power IC as described above, a branch of series-connected sense MOS semiconductor device and resistance (Rs) may be further provided between the first and second output terminals (C,E), such that a sense collector (cs) of the sense MOS semiconductor device is connected to the first output terminal (C), and a sense gate (gs) of the sense MOS semiconductor device is connected to the control input terminal (G). With this arrangement, upon an increase in the potential of the output terminal (C), the potential of the main gate (gm) of the output-stage MOS semiconductor device can be increased without increasing the potential of the gate (gs) of the sense MOS semiconductor device. By separating the main gate (gm) of the output-stage MOS semiconductor device from the sense gate (gs) of the sense MOS semiconductor device, a phase delay of a control circuit system due to a large gate capacity of the output-stage MOS semiconductor device can be avoided, as disclosed in U.S. Pat. No. 5,621,601.
According to the present invention, there is provided a MOS power IC including the depletion type MOS semiconductor device as described above, which comprises: an output-stage MOS semiconductor device including a control portion of a metal-oxide-semiconductor (MOS) structure that provides a main gate (gm) as a control input port, a collector (cm) as an output port, and a main emitter (em); first and second output terminals (C,E) connected to the collector (cm) and the main emitter (em) of the output-stage semiconductor device; a control input terminal (G) connected to the main gate (gm) of the output-stage semiconductor device; an internal control circuit connected between the second output terminal (E) and the control input terminal (G); a turn-off circuit connected between the output terminal (E) and the main gate (gm) of the output MOS semiconductor device; a gate resistance (RG) connected between the main gate (gm) of the output-stage MOS semiconductor device and the control input terminal (G); a depletion type MOS semiconductor device provided between the first output terminal (C) and the main gate (gm) of the output-stage MOS semiconductor device, such that a collector (cd) of the depletion type MOS semiconductor device is connected to the C terminal.
In another form of the MOS power IC, a branch including series-connected depletion type MOS semiconductor device and Zener diode (ZD2) is provided between the first output terminal (C) and the main gate (gm) of the output-stage MOS semiconductor device, such that the collector (cd) of the depletion type MOS semiconductor device is connected to the first output terminal (C), and such that an anode of the Zener diode (ZD2) is connected to the emitter (ed) of the depletion type MOS semiconductor device as shown in FIG. 13.
In a further form of the MOS power IC, a branch in which a depletion type MOS semiconductor device, a Zener diode (ZD2) and a resistance (RCG) are connected in series is provided between the first output terminal (C) and the main gate (gm) of the output-stage MOS semiconductor device, such that the collector (cd) of the depletion type MOS semiconductor device is connected to the first output terminal (C), and such that the anode of the Zener diode (AD2) is connected to the emitter (ed) of the depletion type MOS semiconductor device.
In the above forms of MOS power IC, charger can be injected from the collector (cd) of the depletion type MOS semiconductor device into the main gate (gm) of the output-stage MOS semiconductor device, with small impedance due to (the presence of) the gate resistance (RG), and therefore the turn-on speed can be increased.
In particular, if the resistance (RCG), resistance (RG), and the Zener diode (ZD2) are formed from polysilicon layers that are insulated from the semiconductor substrate, the resulting MOS power IC will not suffer from latch-up of a parasitic thyristor that would occur in the case where these resistances and Zener diode are formed in the semiconductor substrate.
The MOS power IC as described above may further include a Zener diode (ZDl) which is arranged in parallel with the gate resistance (RG), and includes a cathode electrode connected to the control input terminal (G), and an anode electrode connected to the main gate (gm) of the output-stage semiconductor device. With this arrangement, charges can be readily or promptly discharged from the main gate (gm) of the output-stage MOS semiconductor device when it is turned off, and the turn-off time can be reduced.
The MOS power IC as described above may further include a branch in which a Zener diode (ZDl) and a resistance (RZ) are connected in series, which branch is provided in parallel with the gate resistance (RG), such that the anode electrode of the Zener diode (ZDl) is connected to the control input terminal (G), and the cathode electrode is connected to the main gate (gm) of the output-stage semiconductor device. With this arrangement, charges can be promptly discharged from the main gate (gm) of the output-stage MOS semiconductor device when it is turned off, and the turn-off time can be reduced. In addition, the turn-off speed can be adjusted by use of the resistance (RZ).
If the resistance (RZ) and the Zener diode (ZDl) are formed from polysilicon layers that are insulated from a semiconductor substrate, the MOS power IC does not suffer from latch-up of a parasitic thyristor that would occur when these resistance and Zener diode are formed in the semiconductor substrate.
According to the present invention, there is also provided a MOS power IC including the depletion type MOS semiconductor device as described above, which comprises: an output-stage MOS semiconductor device including a control portion of a metal-oxide-semiconductor (MOS) structure that provides a main gate (gm) as a control input port, a collector (cm) as an output port, and a main emitter (em); first and second output terminals (C,E) connected to the collector (cm) and the main emitter (em) of the output-stage semiconductor device; a control input terminal (G) connected to the main gate (gm) of the output-stage semiconductor device; a turn-off circuit connected between the output terminal (E) and the main gate (gm) of the output MOS semiconductor device; a gate resistance (RG) connected between the main gate (gm) of the output-stage MOS semiconductor device and the control input terminal (G); a depletion type MOS semiconductor device including a collector (cd) connected to the first output terminal (C), and an emitter (ed) connected to a circuit power supply terminal (VDD) of an internal control circuit. In another form of the MOS power IC, the collector (cd) of the depletion type MOS semiconductor device is connected to the first output terminal (C), and the emitter (ed) is connected to the cathode electrode of a Zener diode (ZD3), while the anode electrode of the Zener diode (ZD3) is connected to the circuit power supply terminal (VDD) of the internal control circuit as shown in FIG. 15.
In the MOS power ICs as described above, a separate power supply circuit for the internal control circuit need not be provided since power is constantly supplied from the C terminal to the internal control circuit. In the MOS power IC provided with the Zener diode (ZD4), in particular, the leakage current can be prevented when the potential of the control input terminal (G) becomes higher than that of the first output terminal (C).
If the Zener diode (ZD4) is formed from a polysilicon layer that is insulated from the semiconductor substrate, the MOS power IC does not suffer from latch-up of a parasitic thyristor that would occur if the Zener diode is formed in the semiconductor substrate.
The MOS power IC may further includes a Zener diode (AD3) having an anode electrode connected to the control input terminal (G), and a cathode electrode connected to the circuit power supply terminal (VDD) of the internal control circuit. With this arrangement, leakage current can be prevented when the potential of the first output terminal (C) becomes higher than that of the control input terminal (G).
In this case, if the Zener diode (ZD4) is formed from a polysilicon layer that is insulated from the semiconductor substrate, the MOS power IC does not suffer form latch-up of a parasitic thyristor that would occur in the case where the Zener diode is formed in the semiconductor substrate.
According to the present invention, there is also provided a MOS power IC including the depletion type MOS semiconductor device as described above, which comprise: an output-stage MOS semiconductor device including a control portion of a metal-oxide-semiconductor (MOS) structure that provides a main gate (gm) as a control input port, a collector (cm) as an output port, and a main emitter (em); first and second output terminals (C,E) connected to the collector (cm) and the main emitter (em) of the output-stage semiconductor device; a control input terminal (G) connected to the main gate (gm) of the output-stage semiconductor device; an internal control circuit connected between the second output terminal (E) and the control input terminal (G), the internal control circuit including a voltage comparing terminal (VK); a turn-off circuit connected between the second output terminal (E) and the main gate (gm) of the output MOS semiconductor device; a gate resistance (RG) connected between the main gate (gm) of the output-stage MOS semiconductor device and the control input terminal (G); and a depletion type MOS semiconductor device including a collector (cd) connected to the first output terminal (C), and an emitter (ed) connected to the voltage comparing terminal (VK) of the internal control circuit. In another example, the collector (cd) of the depletion type MOS semiconductor device may be connected to the first output terminal (C), and the emitter (ed) of the same device may be connected to the anode of a Zener diode (ZD5), while the cathode of the Zener diode (ZD5) is connected to the voltage comparing terminal of the internal control circuit as shown in FIG. 16.
In the MOS power IC as described above, since the potential of the substrate can be detected by the internal control circuit serving as a comparator, and constant current is produced when the substrate potential is high, steady-slate loss can be reduced as compared with the conventional arrangement using a resistance and a Zener diode. In the MOS power IC provided with the Zener diode (ZD5), in particular, leakage current can be prevented when the potential of the voltage comparing terminal of the internal control circuit becomes higher than that of the first output terminal (C).
If the Zener diode (ZD5) is formed from a polysilicon layer that is insulated from the semiconductor substrate, the MOS power IC does not suffer form latch-up of a parasitic thyristor that would occur in the case where the Zener diode is formed in the semiconductor substrate.
Preferably, the current density of the depletion type MOS semiconductor device surrounded by the pxe2x88x92 well region does not exceed that of the output-stage MOS semiconductor device.
If current flows with a high current density through the depletion type MOS semiconductor device, a potential difference arises within the nxe2x88x92 depletion region and pxe2x88x92 well region, resulting in latch-up of a parasitic thyristor, and a rapidly reduced breakdown voltage.